UCIe and BoW Interconnects for Generative AI on Chiplets
This FAQ compares the performance of BoW and UCIe, exploring how optical interconnects may provide a path to higher performance interconnects in chiplets.
The Bunch-of-Wires (BoW) and Universal Chiplet Interconnect Express (UCIe) standards offer tradeoffs in terms of throughput, interconnect density, delay, and bump pitch.
Designers are turning to chipsets that combine AI accelerators, GPUs, CPU, memory, and networking for optimal performance in generative AI, machine learning, and high-performance computing applications.
Interconnecting heterogeneous devices in a chiplet is challenging, with BoW developed by the Open Domain Specific Architecture (ODSA) working group within the Open Compute Project (OCP) organization.
Designers are turning to chipsets that can combine AI accelerators, GPUs, CPU, memory, and networking in a single package.
Author's summary: UCIe and BoW support generative AI on chiplets.
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